Multiple feedback filter

ABSTRACT

A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

BACKGROUND

Electronic devices, such as personal electronic devices, robots,electric cars, industrial equipment, medical equipment and wearabledevices, utilize filters to attenuate undesired signals, such asinterferers. Basically, “analog filters” operate in the frequency domainand attenuate frequencies that are “out of band”. For example, low-passfilters attenuate frequencies above a certain frequency and passfrequencies (for example with little to no attenuation) below thatcertain frequency. The band of frequencies that are passed through thefilter with little to no attenuation is referred to as the “pass band”.Other types of “analog filters” includes band-pass filters (wherefrequencies above and below a certain pass band are attenuated),high-pass filters (where frequencies below a certain frequency areattenuated) and band-stop filters (where frequencies in a certain bandare attenuated). The band-stop filters are also referred to as notchfilters.

Each of these analog filters may be implemented using only passivecomponents, such as resistors, capacitors and/or inductors, or a mixtureof active components, such as amplifiers (e.g. operational amplifiers)and/or transistors, and passive components. Both passive and activefilters may have issues with pass band characteristics (e.g. how flat isthe pass band, is the pass band too attenuated, does the pass band covera sufficient frequency band); out-of-band characteristics (does thefilter sufficiently attenuate out-of-band frequencies, especially thoseclose to the pass band); and characteristics of the components used toimplement the filter (are large capacitors and/or resistors required,are there conditions where the amplifier becomes unstable, is too muchpower consumed by the filter).

In addition to the above, the quality factor (“Q”) of filters that aresecond order or higher is also an important indicia of the performanceof the filter. The quality factor of a filter is an indication of thepass band attenuation/gain, the width of the pass band and the rate inwhich the magnitude of out-of-band roll-off occurs. For example, asecond order low-pass filter with a low Q value will have a slow rolloff for frequencies above the cut-off frequency, f_(c). Whereas a secondorder low-pass filter with a high Q value will have a steeper roll offbut may have a peak at (or near) the cut-off frequency.

SUMMARY

An example embodiment includes a circuit having an input and an output,the circuit comprising: a first amplifier having a first input, a secondinput and an output coupled to the output of the circuit; a firstcapacitor having a first terminal coupled to the first input of thefirst amplifier and a second terminal coupled to the output of the firstamplifier; a first resistor having a first terminal coupled to the firstinput of the first amplifier and a second terminal; a buffer having anoutput coupled to the second terminal of the first resistor and aninput; a second resistor having a first terminal coupled to the outputof the first amplifier and a second terminal coupled to the input of thebuffer; a second capacitor coupled between the input of the buffer andground; and a third resistor coupled between the input of the buffer andthe input of the circuit. In an example embodiment, the circuit is alow-pass filter. The second input of the first amplifier is coupled to areference voltage. The first capacitor has a first capacitance value andthe second capacitor has a second capacitance value that can besubstantially equal to or different from the first capacitance value. Inan alternative example embodiment, the buffer includes a secondamplifier having a first input connected to the second terminal of thesecond resistor, a second input and an output connected to the secondinput and to the second terminal of the first resistor.

An alternative embodiment includes a circuit having an input and anoutput, the circuit comprising: a first amplifier having a first input,a second input and an output coupled to the output of the circuit; afirst capacitor having a first terminal coupled to the first input ofthe first amplifier and a second terminal coupled to the output of thefirst amplifier; a first resistor having a first terminal coupled to thefirst input of the first amplifier and a second terminal; a secondamplifier having a first input, a second input and an output connectedto the second input and to the second terminal of the first resistor; asecond resistor having a first terminal coupled to the output of thefirst amplifier and a second terminal coupled to the first input of thesecond amplifier; a second capacitor coupled between the first input ofthe second amplifier and ground; and a third resistor coupled betweenthe first input of the second amplifier and the input of the circuit.The circuit is a low-pass filter, and the second input of the firstamplifier is coupled to a reference voltage. The first capacitor has afirst capacitance value and the second capacitor has a secondcapacitance value that can be substantially equal to or different fromthe first capacitance value.

Another alternative embodiment includes a circuit having an input and anoutput, the circuit comprising: a first amplifier having a first input,a second input and an output coupled to the output of the circuit; afirst super source follower (SSF) circuit having an input connected to areference voltage and an output connected to the second input of thefirst amplifier; a first capacitor having a first terminal coupled tothe first input of the first amplifier and a second terminal coupled tothe output of the first amplifier; a first resistor having a firstterminal coupled to the first input of the first amplifier and a secondterminal; a second SSF circuit having an input and an output connectedto the second terminal of the first resistor; a second resistor having afirst terminal coupled to the output of the first amplifier and a secondterminal coupled to the input of the second SSF circuit; a secondcapacitor coupled between the input of the second SSF circuit andground; and a third resistor coupled between the input of the second SSFcircuit and the input of the circuit. The circuit is a low-pass filter,the first capacitor has a first capacitance value and the secondcapacitor has a second capacitance value that can be substantially equalto or different from the first capacitance value. In another alternativeembodiment, the second SSF circuit includes: a first transistor having afirst control terminal connected to the input of the second SSF circuit,a first current terminal and a second current terminal; a secondtransistor having a second control terminal connected to the firstcurrent terminal, a third current terminal connected to a first supplyrail and a fourth current terminal connected to the second currentterminal and the output of the second SSF circuit; a first currentsource connected between the second current terminal and a second supplyrail; and a second current source connected between the first supplyrail and the first current terminal. The first transistor is an nMOSFET,and the second transistor is a pMOSFET. The second supply rail isground.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of various examples, reference will now bemade to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a filter of an example embodiment.

FIG. 2 is a schematic diagram of a filter of an example embodiment thatutilizes a buffer.

FIG. 3A and FIG. 3B are schematic diagrams of a filter of an exampleembodiment that utilizes different example buffers.

FIG. 3C is a schematic diagram of a super source follower of an exampleembodiment.

Features with the same reference numeral or identifier are intended tobe similar features.

DETAILED DESCRIPTION

An example embodiment includes a multiple feedback (“MFB”) filter thatis less sensitive to component variations and/or size than aconventional filter. Some example embodiments also include a buffer orsuper source follower (“SSF”) coupled to one or both inputs of anamplifier used in the filter. In some example embodiments, the filter isa MFB filter, which is a second order low-pass filter.

Referring to FIG. 1, low-pass filter 100 is a second order MFB filterthat uses resistors R₁, R₂ and R₃, capacitors C₁ and C₂ and amplifier102. Resistor R₁ is connected between the input signal, V_(IN), and node106. The voltage at node 106 is V_(X). Resistor R₂ is connected betweennode 106 and the inverting (also referred to as the “negative”) input(node 108) of amplifier 102. The non-inverting (also referred to as the“positive”) input of amplifier 102 is connected to reference voltageV_(CM) (also referred to as the common mode voltage), and the output ofamplifier 102 provides the output (V_(OUT)) of filter 100. Capacitor C₁is connected between node 106 and ground 104, and capacitor C₂ isconnected between the inverting input (node 108) of amplifier 102 andthe output of amplifier 102. Resistor R₃ is connected between node 106and the output of amplifier 102.

In operation, filter 100 filters V_(IN) so that the higher frequencycomponents of V_(IN) are attenuated at V_(OUT). The transfer function offilter 100 is provided by:

$\begin{matrix}{\frac{V_{OUT}}{V_{IN}} = {- \frac{\frac{G_{1}}{G_{3}}}{{S^{2}\frac{C_{1}C_{2}}{G_{2}G_{3}}} + {S\frac{C_{2}\left( {G_{1} + G_{2} + G_{3}} \right)}{G_{2}G_{3}}} + 1}}} & (1)\end{matrix}$

where G₁=1/R₁, G₂=1/R₂ and G₃=1/R₃. The DC gain, A; pole frequency,ω_(o); and the quality factor, Q, for filter 100 can be calculated usingequations (2).

$\begin{matrix}{{{A = {G_{1}/G_{3}}}{\omega_{o} = \sqrt{\frac{G_{2}G_{3}}{C_{1}C_{2}}}}Q} = {\frac{\sqrt{G_{2}G_{3}}}{G_{1} + G_{2} + G_{3}} \cdot \sqrt{\frac{C_{1}}{C_{2}}}}} & (2)\end{matrix}$

As is shown below in equation (3), the value for the quality factor forfilter 100 is limited by the ratio of capacitors C₁ to C₂, regardless ofthe ratio of resistors G₂ to G₃.

$\begin{matrix}{Q = {{{\frac{\sqrt{\frac{G_{2}}{G_{3}}}}{\frac{G_{1}}{G_{3}} + \frac{G_{2}}{G_{3}} + 1} \cdot \sqrt{\frac{C_{1}}{C_{2}}}}x}\overset{x = \sqrt{\frac{G_{2}}{G_{3}}}}{\Rightarrow}{{\frac{x}{\left( {A + 1} \right) + x^{2}} \cdot \sqrt{\frac{C_{1}}{C_{2}}}} \leq {\frac{1}{2\sqrt{A + 1}}\sqrt{\frac{C_{1}}{C_{2}}}}}}} & (3)\end{matrix}$

In order to implement filter 100 with the desired quality factor(especially sufficiently high Q), there must be a requirement on theminimum value for the ratio of capacitors C₁ to C₂, given by:

$\begin{matrix}{\frac{C_{1}}{C_{2}} \geq {4\left( {A + 1} \right)Q^{2}}} & (4)\end{matrix}$

As is apparent from equation (4), for a low quality factor (Q<1), thesize of capacitors C₁ and C₂ can be modest (which is easilyimplemented). However, in order to realize a sufficiently high qualityfactor (e.g. Q>1), the capacitance (and, along with that, the size) ofcapacitor C₁ should be quite high. For example, according to equation(4), for a quality factor (Q) of 2.5 and a filter DC gain (A) of 1, theratio of capacitors C₁ to C₂ would be greater than 50. Therefore, if C₂was 0.5 pF, the minimum capacitance value for C₁ would be greater than25 pF. A capacitor this large would require a lot of active area if itwas implemented in a semiconductor device. Hence, this size of capacitoris difficult to implement using standard semiconductor processing anddevice structures.

Referring to FIG. 2, in another example embodiment a buffer (e.g. avoltage buffer or a unity gain amplifier) is added to low-pass filter100 to form low-pass filter 200 (e.g. a second-order low-pass filter).The input (signal, V_(X)) of buffer 202 is connected to node 106 and theoutput (signal, V_(Y)) of buffer 202 is connected to the inverting input(node 108) of amplifier 102 through resistor R₂. The transfer functionof filter 200 is:

$\begin{matrix}{\frac{V_{OUT}}{V_{IN}} = {- \frac{\frac{G_{1}}{G_{3}}}{{S^{2}\frac{C_{1}C_{2}}{G_{2}G_{3}}} + {S\frac{C_{2}\left( {G_{1} + G_{3}} \right)}{G_{2}G_{3}}} + 1}}} & (5)\end{matrix}$

where G₁=1/R₁, G₂=1/R₂ and G₃=1/R₃. Compared to the transfer function offilter 100 in equation (1), only the ‘s’ term in the denominator ischanged. The DC gain, A; pole frequency (ω_(o)=2πf_(o)); and the qualityfactor, Q, for filter 200 are provided below in equations (6):

$\begin{matrix}{{{A = {G_{1}/G_{3}}}{\omega_{o} = \sqrt{\frac{G_{2}G_{3}}{C_{1}C_{2}}}}Q} = {\frac{\sqrt{G_{2}G_{3}}}{G_{1} + G_{3}} \cdot \sqrt{\frac{C_{1}}{C_{2}}}}} & (6)\end{matrix}$

The DC gain and the pole frequency equations for filter 200 are the sameas the DC gain and pole frequency equations for filter 100 (equation(2)). However, with the addition of buffer 202 the equation for thequality factor for filter 200 is different than the equation for thequality factor for filter 100. Specifically, since little to no currentflows into the input of buffer 202, the portion of the transfer functionrelating to current through resistor R₂ (i.e. G₂*V_(X)) is eliminated inKirchhoff s Current Law equation at node 106, and, hence, in the ‘s’term of the denominator of equation (5) C₂ is multiplied by (G₁+G₃)instead of (G₁+G₂+G₃). According to equation (6) for the quality factorfor filter 200, there is no constraint between the achievable qualityfactor Q and the ratio of capacitors C₁ to C₂. Therefore, the ratio ofcapacitors C₁ to C₂ can be flexibly chosen (as small as just 1) infilter 200, and the desired Q is realized with appropriate value for theratio of resistors G₂ to G₃. For example, where the quality factor (Q)is around 2.5 and the DC gain (A) is 1, the ratio of C₁ to C₂ is greaterthan around 50 for filter 100 but can be chosen to be 1 for filter 200.Hence, if a 0.5 pF capacitor is used for C₂ then C₁ would need to begreater than 25 pF for filter 100 but only around 0.5 pF for filter 200.The total capacitance size of capacitors C₁ and C₂ for filter 200 isreduced compared to that for filter 100, which results in a significantreduction of active area if implemented in a semiconductor device.

In another example embodiment, equations (7), (8) and (9) are used todetermine the values of resistors R₁, R₂ and R₃ for filter 200,respectively.

$\begin{matrix}{G_{1} = \frac{{Ar}\;\omega_{o}C_{2}}{\left( {A + 1} \right)Q}} & (7) \\{G_{2} = {\left( {A + 1} \right)Q\omega_{o}C_{2}}} & (8) \\{G_{3} = \frac{r\;\omega_{o}C_{2}}{\left( {A + 1} \right)Q}} & (9)\end{matrix}$

where r=C₁/C₂. For example, in an example embodiment where the DC gain(A) is 1, the quality factor (Q) is around 2.5, the pole frequency(ω_(o)) is around 52 MHz, and C₁ and C₂ are 0.5 pF (as stated above): R₁is around 31 kΩ, R₂ is around 1.2 kΩ and R₃ is around 31 kΩ.

The transfer function of V_(X) to V_(IN) for filter 200 is shown inequation (10).

$\begin{matrix}{\frac{V_{X}}{V_{IN}} = \frac{S\;\frac{C_{2}G_{1}}{G_{2}G_{3}}}{{S^{2}\frac{C_{1}C_{2}}{G_{2}G_{3}}} + {S\frac{C_{2}\left( {G_{1} + G_{3}} \right)}{G_{2}G_{3}}} + 1}} & (10)\end{matrix}$

Equation (10) illustrates that the peak gain for filter 200 occurs atthe pole frequency, ω_(o). The peak gain is shown in equation (11).

$\begin{matrix}{{\frac{V_{X}}{V_{IN}}@\omega_{o}} = {\frac{G_{1}}{G_{1} + G_{3}} = \frac{A}{A + 1}}} & (11)\end{matrix}$

Based on equations (10) and (11), the voltage at node 106 of filter 200should not appreciably vary with respect to V_(IN).

FIGS. 3A and 3B illustrate example implementations of the exampleembodiment of FIG. 2. Specifically, filter 300 of FIG. 3A utilizes anamplifier 302 (e.g. an operation amplifier) with the output of amplifier302 connected to the inverting input of amplifier 302 in place of buffer202. Filter 310 of FIG. 3B utilizes one or more (two are shown in theexample embodiment of FIG. 3B) super source follower (“SSF”) circuits.In the example embodiment of FIG. 3B, an SSF 312 is connected betweennode 106 and resistor R₂. Since a voltage shift may occur between theinput of SSF 312 and the output of SSF 312 (hence a shift in voltage ofV_(Y) with respect to V_(X)), an additional SSF may be connected to thenon-inverting input of amplifier 102 in this example embodiment toaccount for this voltage shift. Specifically, SSF 314 (which may or maynot be the same as SSF 312 in sizing of transistors and bias currents)is connected between reference voltage source V_(CM) and thenon-inverting input of amplifier 102. The transfer functions of filters300 and 310 should be the same as shown in equations (5).

FIG. 3C illustrates an example implementation of SSF 312 and SSF 314.Node 330 of SSF 313 may be connected to node 106 for SSF 312 or V_(CM)for SSF 314. Node 332 of SSF 313 may be connected to resistor R₂ for SSF312 or the non-inverting input of amplifier 102 for SSF 314. SSF 313includes transistors 322 and 320. The gate of transistor 322 isconnected to node 330, the source is connected to node 332 and to ground104 through current source 324 and the drain is connected to node 334and to voltage supply 316 through current source 318. The gate oftransistor 320 is connected to node 334. The source of transistor 320 isconnected to voltage supply 316 and the drain is connected to node 332.While transistors 320 and 322 are shown in FIG. 3C asmetal-oxide-silicon field-effect transistors (“MOSFETs”), transistors320 and/or 322 can be bipolar junction transistors, junctionfield-effect transistors or other type of transistor. In addition,transistors 320 is shown as a pMOSFET but it can be n-type, andtransistor 322 is shown to be an nMOSFET but it can be p-type.

While the capacitors of low-pass filters 200, 300 and 310 can be smaller(both in terms of capacitance values and physical size) than those usedin low-pass filter 100, these filters, in some example embodiments, mayconsume less power than low-pass filter 100. If amplifier 102 was ideal,it would have an infinite gain-bandwidth product (“GBW”). However, ifamplifier 102 is not ideal, it will have a finite GBW. If the GBW of theamplifier used in the filter is lower, the performance of the filtersuffers. Specifically, the filter magnitude response (filteringcharacteristic) is changed from the ideal filter transfer function ifthe amplifier GBW is lower. To maintain the magnitude response of thefilter in these instances, greater power is consumed by the filter, ashigher amplifier GBW corresponds to higher power consumption inamplifier 102. Since filters 200, 300 and 310 are impacted less by theGBW of the amplifier 102 (as compared to filter 100), namely, tomaintain the same degradation of filter magnitude response from theideal at an acceptable level, the amplifier GBW requirement in thesefilters 200, 300 and 310 is significantly reduced to around half of thatin filter 100, therefore these filters require less power (maybe aslittle as half the power as required in filter 100).

In the foregoing discussion and in the claims, the terms “including” and“comprising” are used in an open-ended fashion, and thus should beinterpreted to mean “including, but not limited to . . . .” An elementor feature that is “configured to” perform a task or function may beconfigured (e.g., programmed or structurally designed) at a time ofmanufacturing by a manufacturer to perform the function and/or may beconfigurable (or re-configurable) by a user after manufacturing toperform the function and/or other additional or alternative functions.The configuring may be through firmware and/or software programming ofthe device, through a construction and/or layout of hardware componentsand interconnections of the device, or a combination thereof.Additionally, uses of the phrases “ground” or similar in the foregoingdiscussion are intended to include a chassis ground, an Earth ground, afloating ground, a virtual ground, a digital ground, a common ground,and/or any other form of ground connection applicable to, or suitablefor, the teachings of the present disclosure. Unless otherwise stated,“approximately” preceding a value means +/−10 percent of the statedvalue. As used herein, the term “modulate” shall also mean “to vary” or“to change.” The terms “node”, “terminal”, “pin” and “interconnection”,for example, are interchangeably used and referred to any connection (orinterconnection) between features. These terms are not meant to belimiting with respect to a certain type of physical structure. Forexample, the “terminals” of a circuit element are meant to be eachconnection to such circuit element. Hence, an integrated resistor wouldbe referred to have two terminals (ends) even though these “terminals”are just the two connections to the integrated resistor.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present disclosure. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. A circuit having an input and an output, thecircuit comprising: a first amplifier having a first input, a secondinput and an output coupled to the output of the circuit; a firstcapacitor having a first terminal coupled to the first input of thefirst amplifier and a second terminal coupled to the output of the firstamplifier; a first resistor having a first terminal coupled to the firstinput of the first amplifier and a second terminal; a buffer having anoutput coupled to the second terminal of the first resistor and aninput; a second resistor having a first terminal coupled to the outputof the first amplifier and a second terminal coupled to the input of thebuffer; a second capacitor coupled between the input of the buffer andground; and a third resistor coupled between the input of the buffer andthe input of the circuit.
 2. The circuit of claim 1, wherein the circuitis a low-pass filter.
 3. The circuit of claim 1, wherein the secondinput of the first amplifier is coupled to a reference voltage.
 4. Thecircuit of claim 1, wherein the first capacitor has a first capacitancevalue and the second capacitor has a second capacitance value that issubstantially equal to the first capacitance value.
 5. The circuit ofclaim 1, wherein the buffer includes a second amplifier having a firstinput connected to the second terminal of the second resistor, a secondinput and an output connected to the second input and to the secondterminal of the first resistor.
 6. A circuit having an input and anoutput, the circuit comprising: a first amplifier having a first input,a second input and an output coupled to the output of the circuit; afirst capacitor having a first terminal coupled to the first input ofthe first amplifier and a second terminal coupled to the output of thefirst amplifier; a first resistor having a first terminal coupled to thefirst input of the first amplifier and a second terminal; a secondamplifier having a first input, a second input and an output connectedto the second input and to the second terminal of the first resistor; asecond resistor having a first terminal coupled to the output of thefirst amplifier and a second terminal coupled to the first input of thesecond amplifier; a second capacitor coupled between the first input ofthe second amplifier and ground; and a third resistor coupled betweenthe first input of the second amplifier and the input of the circuit. 7.The circuit of claim 6, wherein the circuit is a low-pass filter.
 8. Thecircuit of claim 6, wherein the second input of the first amplifier iscoupled to a reference voltage.
 9. The circuit of claim 6, wherein thefirst capacitor has a first capacitance value and the second capacitorhas a second capacitance value that is substantially equal to the firstcapacitance value.
 10. A circuit having an input and an output, thecircuit comprising: a first amplifier having a first input, a secondinput and an output coupled to the output of the circuit; a first supersource follower (SSF) circuit having an input connected to a referencevoltage and an output connected to the second input of the firstamplifier; a first capacitor having a first terminal coupled to thefirst input of the first amplifier and a second terminal coupled to theoutput of the first amplifier; a first resistor having a first terminalcoupled to the first input of the first amplifier and a second terminal;a second SSF circuit having an input and an output connected to thesecond terminal of the first resistor; a second resistor having a firstterminal coupled to the output of the first amplifier and a secondterminal coupled to the input of the second SSF circuit; a secondcapacitor coupled between the input of the second SSF circuit andground; and a third resistor coupled between the input of the second SSFcircuit and the input of the circuit.
 11. The circuit of claim 10,wherein the circuit is a low-pass filter.
 12. The circuit of claim 10,wherein the first capacitor has a first capacitance value and the secondcapacitor has a second capacitance value that is substantially equal tothe first capacitance value.
 13. The circuit of claim 10, wherein thesecond SSF circuit includes: a first transistor having a first controlterminal connected to the input of the second SSF circuit, a firstcurrent terminal and a second current terminal; a second transistorhaving a second control terminal connected to the first currentterminal, a third current terminal connected to a first supply rail anda fourth current terminal connected to the second current terminal andthe output of the second SSF circuit; a first current source connectedbetween the second current terminal and a second supply rail; and asecond current source connected between the first supply rail and thefirst current terminal.
 14. The circuit of claim 13, wherein the firsttransistor is an nMOSFET.
 15. The circuit of claim 13, wherein thesecond transistor is a pMOSFET.
 16. The circuit of claim 13, wherein thesecond supply rail is ground.